Submission and Web Chair:
- Giovanni Agosta, POLIMI, IT
- João M.P. Cardoso, UPorto, PT
- William Fornanciari, POLIMI, IT
- Michael Hübner, B-TU, DE
- Cristina Silvano, POLIMI, IT
- Dimitrios Soudris, NTUA, GR
- Jeronimo Castrillon, TU Dresden, DE
- Alessandro Cilardo, University of Naples Federico II, IT
- Biagio Cosenza, University of Salerno, IT
- Damien Couroussé, CEA, FR
- Andrés Goens, University of Edinburgh, UK
- Frank K. Gürkaynak, Microelectronic Design Center - ETH Zürich, CH
- Carles Hernandez Luz, Universitat Politècnica de València, ES
- Raquel Lazcano, Università degli Studi di Sassari, IT
- Francesco Leporati, University of Pavia, IT
- Daniel Madroñal, Università degli Studi di Sassari, IT
- Vittoriano Muttillo, University of L'Aquila, IT
- Luigi Pomante, University of L'Aquila, IT
- Mario Porrmann, Osnabrueck University, DE
- Marco Procaccini, University of Siena, IT
- Alfonso Rodriguez, Universidad Politécnica de Madrid, ES
- Benjamin Rouxel, University of Amsterdam, NL
- Ruben Salvador, CentraleSupélec - IETR, FR
- Olivier Sentieys, INRIA, FR
- Leonel Sousa, Universidade de Lisboa, PT
- Sander Stuijk, Eindhoven University of Technology, NL
- Massimo Torquati, University of Pisa, IT
- Sotirios Xydis, National Technical University of Athens, GR
- Pablo de Oliveira Castro, University of Versailles Saint-Quentin-en-Yvelines, FR
Toulouse, FR, 17/01/2023
Co-located with HiPEAC
Scope of the Workshop
The current trend towards many-core and the emerging accelerator-based architecture requires a global rethinking of software and hardware design, which turn out to be more than ever before strongly entangled.
The PARMA-DITAM workshop focuses on many-core architectures, parallel programming models, design space exploration, tools and run-time management techniques to exploit the features and boost the performance of such (possibly heterogeneous, (re-)programmable and/or (re-)configurable) many-core processor architectures from embedded to high performance computing platforms and cyber physical systems.
The PARMA-DITAM workshop will have seven main topics:
- T1: Parallel programming models and languages, compilers and virtualization techniques
- T2: Runtime modelling, monitoring, adaptivity, and management
- T3: Runtime trade-off execution, power management, and memory management
- T4: Heterogeneous and reconfigurable many-core: architectures and design space exploration
- T5: Methodologies, design tools, and high level synthesis for many-core architectures
- T6: Parallel applications for many-core platforms
- T7: Case studies, success stories and applications applying T1-T6
11/11/2022 - 11:59 PM (UTC): Paper Submission Deadline 15/11/2022 - 11:59 PM (UTC): Paper Submission Deadline
- 27/11/2022 - 11:59 PM (UTC): NEW EXTENDED Paper Submission Deadline
09/12/2022: Acceptance Notification
- 16/12/2022: (EXTENDED deadline) Acceptance Notification
- 31/12/2022: Camera ready version of accepted papers for workshop proceedings
Information for Authors:
Paper submission: Papers should be submitted electronically through the workshop website in PDF format. The review process will be double-blind. Only full papers are accepted.
All submissions are required to respect the following guidelines:
- Length: Up to 10 pages single column, excluding title page and references.
- Template: Please use the OASIcs template when preparing your manuscript.
See Camera Ready Submission Guidelines for additional details.
Paper presentation: At least one author per accepted paper should present their work during the workshop. We invite authors of accepted papers to prepare presentations with slides. Each paper presentation is scheduled to last at most 15 minutes.
Time slot includes: 10 min oral presentation + 3 min Q&A + 2 min technical setup & speaker introduction by Session chair.
Presenters should provide a short (no more than 3 lines) biography introduction to be handed to the Session chair at the beginning of the Session. We additionally encourage presenters to prepare a PDF version of their slide to be uploaded on the workshop website.