PARMA-DITAM 2025 Workshop

General Chair:

Program Co-Chair:

Program Co-Chair:

Publicity Chair:

Publication Chair:

Submission and Web Chair:

Steering Committee:

Program Committee

  • Luis Costero, Universidad Complutense de Madrid, ES
  • Damien Couroussé, CEA, FR
  • Kim Gruettner, German Aerospace Center, DE
  • Frank K. Gürkaynak, ETH Zürich, CH
  • Carles Hernandez, Universitat Politècnica de València, ES
  • Francesco Leporati, University of Pavia, IT
  • Manolis Marazakis, FORTH Institute of Computer Science, Heraklion, GR
  • Dimosthenis Masouros, National Technical University of Athens, GR
  • Konstantina Mitropoulou, AMD
  • Luigi Pomante, University of L'Aquila, IT
  • Mario Porrmann, Osnabrueck University, DE
  • Marco Procaccini, University of Siena, IT
  • Alfonso Rodriguez, Universidad Politécnica de Madrid, ES
  • Ruben Salvador, CentraleSupélec – IETR, FR
  • Leonel Sousa, Universidade de Lisboa, PT
  • Sander Stuijk, Eindhoven University of Technology, NL
  • Massimo Torquati, University of Pisa, IT

Barcelona, ES, 22/01/2025

Co-located with HiPEAC


Scope of the Workshop

The current trend towards many-core and heterogeneous accelerator-based architectures requires a global rethinking of software and hardware design, which turn out to be more than ever before strongly entangled.

The PARMA-DITAM workshop focuses on many-core architectures, parallel programming models, design space exploration, run-time management techniques, tools and methodologies designed to fully exploit many-core processor architectures (possibly heterogeneous and reconfigurable) and boost their performance, from embedded to high performance computing platforms and cyber-physical systems.


The PARMA-DITAM workshop will have seven main topics:

  • T1: Parallel programming models, languages, and applications for many-core platforms
  • T2: Compiler and virtualization techniques for novel computing architectures
  • T3: Run-time modeling, monitoring, adaptivity, power and memory management
  • T4: Design of heterogeneous and reconfigurable many-core architectures
  • T5: Methodologies, design tools, and high-level synthesis for heterogeneous architectures
  • T6: Hardware/software co-design and design space exploration
  • T7: Case studies, success stories and applications applying T1-T6

Important Dates:

  • 17/11/2024 - 23:59 (UTC): Paper Submission Deadline
  • 03/12/2024 - 23:59 (UTC): Paper Submission Deadline
  • 09/12/2024 - 23:59 (UTC): NEW EXTENDED Paper Submission Deadline
  • 13/12/2024: Acceptance Notification
  • 22/12/2024: (EXTENDED deadline) Acceptance Notification
  • 23/12/2024 - 23:59 (UTC): Camera ready version of accepted papers for workshop proceedings
  • 08/01/2025 - 23:59 (UTC): (EXTENDED deadline) Camera ready version of accepted papers for workshop proceedings

Information for Authors:

Paper submission: Papers should be submitted electronically through EasyChair in PDF format. The review process will be single-blind. Only full papers are accepted.

Submission Website

All submissions are required to respect the following guidelines:

  • Length: Up to 10 pages single column, excluding title page and references.
  • Template: Please use the OASIcs template when preparing your manuscript.
Accepted papers will be provided a DOI, and published online in the Dagstuhl OASIcs OpenAccess Series in Informatics.

See Camera Ready Submission Guidelines for additional details.


Camera Ready preparation instructions: The camera ready version of the accepted papers should be submitted up to 23/12/2024 08/01/2025 and be prepared according to the guidelines summarized in the following link: Camera Ready Submission Guidelines.